This invention relates, in general, to semiconductor packages, and more particularly to a ceramic semiconductor package having metal crack arrestor patterns strategically disposed therein.
It is well known in the semiconductor art that high quality semiconductor device packages may be manufactured from composite ceramic materials. Ceramics are especially useful in relatively large packages such as those used in pin grid arrays, leadless chip carriers, dual-in-line side brazed packages and the like. These ceramic packages may be comprised of a single layer of ceramic material or multiple layers of ceramic material that are bonded together Generally, the ceramic layers are fabricated in a predetermined manner so that metal interconnect lines may be formed thereon. Tungsten alloys and other like metals are commonly used to form the interconnect lines. Ceramic semiconductor packages having multiple bonded ceramic layers as well as multiple layers of interconnect lines disposed thereon are well known in the art.
Generally, because ceramics are composite materials, the density of the material is not uniform throughout. Porosity and grain boundaries in the material allow for microcrack formation throughout the ceramic. The microcracks propagate within the ceramic and are not restricted until they encounter metal such as that used in interconnect lines and vias. Microcracking may occur in an exceptionally high number of composite ceramic semiconductor packages thereby causing relatively low yields and device lifetimes. Therefore, a composite ceramic semiconductor package that reduces or restricts microcracking throughout is highly desirable.